1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a porous insulating layer and a manufacturing method thereof
2. Description of the Background Art
In recent years, in order to achieve high performance of a semiconductor device, a technique to lower interconnection resistance and capacitance between interconnections has been developed. Forming of a copper interconnection has been known as one technique to lower interconnection resistance. Here, as the copper interconnection is formed in an interlayer insulating film, an interlayer insulating film having low dielectric constant should be employed, in order to lower interconnection capacitance. Various techniques employing a porous material for the interlayer insulating film of low dielectric constant have been proposed (see, for example, Japanese Patent Laying-Open Nos. 2004-221498, 2004-158704, and 2006-041039).
Meanwhile, porous silica has been known as a porous material having low dielectric constant, high mechanical strength and high insulation (see, for example, Japanese Patent Laying-Open Nos. 2004-292304 and 2005-272188). The porous silica can be obtained by preparing and applying a coating liquid followed by drying and annealing.
If porous silica above is used for the interlayer insulating film of the semiconductor device, however, the following problems arise.
In forming, with etching, a via and a trench for interconnection communicating to the via in the interlayer insulating film formed as a single layer of porous silica, control of depth of the trench for interconnection during etching is difficult. In addition, when etching should be suspended, etching causes damage of porous silica at the bottom of the trench for interconnection, which leads to increase in a leakage current and higher dielectric constant in that portion.
In order to facilitate control of depth of the trench for interconnection, it is also possible to employ a stack structure of another insulating layer and porous silica as the interlayer insulating film, and to form a via and a trench for interconnection in another insulating layer and porous silica, respectively. In such a case, however, annealing for forming porous silica causes increase in the leakage current and higher dielectric constant in another insulating layer.